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(ds8582 rev. n) 03/07 hi-8582, hi-8583 pin configuration (top view) hi-8582pqi hi-8582pqt & hi-8583pqi hi-8583pqt 52 - 51 - rin2b 50 - rin2a 49 - rin1b 48 - rin1a 47 - vdd 46 - n/c 45 - test 44 - 43 - txclk 42 - clk 41 - 40 - n/c d/r1 mr rsr 39 - n/c 38 - 37 - entx 36-v+ 35 - txbout 34 - txaout 33-v- 32 - 31 - 30 - tx/r 29 - 28 - 27 - bd00 cwstr fft hft pl2 pl1 bd10 - 14 bd09 - 15 bd08 - 16 bd07 - 17 bd06 - 18 n/c-19 gnd-20 -21 bd05 - 22 bd04 - 23 bd03 - 24 bd02 - 25 bd01 - 26 nfd ff1 hf1 d/r2 ff2 hf2 en1 en2 -1 -2 -3 -4 -5 sel - 6 -7 -8 bd15 - 9 bd14 - 10 bd13 - 11 bd12 - 12 bd11 - 13 general description the hi-8582/hi-8583 from holt integrated circuits are a silicon gate cmos devices for interfacing a 16-bit parallel data bus directly to the arinc 429 serial bus. the hi-8582/hi-8583 design offers many enhancements to the industry standard hi-8282 architecture. the device provides two receivers each with label recognition, 32 by 32 fifo, and analog line receiver. up to 16 labels may be programmed for each receiver. the independent transmit- ter has a 32 x 32 fifo and a built-in line driver. the status of all three fifos can be monitored using the external status pins, or by polling the hi-8582/hi-8583 status register. other new features include a programmable option of data or parity in the 32nd bit, and the ability to unscramble the 32 bit word. also, versions are available with different values of input resistance and output resistance to allow users to more easily add external lightning protection circuitry. the device can be used at nonstandard data rates when an option pin, , is invoked. the 16-bit parallel data bus exchanges the 32-bit arinc data word in two steps when either loading the transmitter or interrogating the receivers. the databus and all control signals are cmos and ttl compatible. the hi-8582/hi-8583 apply the arinc protocol to the receivers and transmitter. timing is based on a 1 mega- hertz clock. although the line driver shares a common substrate with the receivers, the design of the physical isolation does not allow parasitic crosstalk, and thereby achieves the same isolation as common hybrid layouts. nfd applications avionics data communication serial to parallel conversion parallel to serial conversion features arinc specification 429 compatible dual receiver and transmitter interface programmable label recognition 32 x 32 fifos each receiver and transmitter status register data scramble control 32nd transmit bit can be data or parity self test mode low power industrial & full military temperature ranges analog line driver and receivers connect directly to arinc bus on-chip 16 label memory for each receiver independent data rate selection for transmitter and each receiver 52 - pin plastic quad flat pack (pqfp) (see page 14 for additional pin configuration) march 2007 arinc 429 system on a chip holt integrated circuits www.holtic.com
pin descriptions signal function description vdd power +5v % bd05 i/o data bus bd04 i/o data bus bd03 i/o data bus bd02 i/o data bus 5 rin1a input arinc receiver 1 positive input rin1b input arinc receiver 1 negative input rin2a input arinc receiver 2 positive input rin2b input arinc receiver 2 negative input output receiver 1 data ready flag output fifo full receiver 1 output fifo half full, receiver 1 output receiver 2 data ready flag output fifo full receiver 2 output fifo half full, receiver 2 sel input receiver data byte selection (0 = byte 1) (1 = byte 2) input data bus control, enables receiver 1 data to outputs input data bus control, enables receiver 2 data to outputs if is high bd15 i/o data bus bd14 i/o data bus bd13 i/o data bus bd12 i/o data bus bd11 i/o data bus bd10 i/o data bus bd09 i/o data bus bd08 i/o data bus bd07 i/o data bus bd06 i/o data bus gnd power 0 v bd01 i/o data bus bd00 i/o data bus input latch enable for byte 1 entered from data bus to transmitter fifo. input latch enable for byte 2 entered from data bus to transmitter fifo. must follow tx/r output transmitter ready flag. goes low when arinc word loaded into fifo. goes high after transmission and fifo empty. output transmitter fifo half full output transmitter fifo full v- power -9.5v to -10.5v txaout output line driver output - a side txbout output line driver outpu t - b side v+ power +9.5v to +10.5v entx input enable transmission input clock for control word register input read status register if sel=0, read control register if sel=1 input no frequency discrimination if low (pull-up) clk input master clock input tx clk output transmitter clock equal to master clock (clk), divided by either 10 or 80. input master reset, active low test input disable transmitter output if high (pull-down) d/r1 ff1 hf1 d/r2 ff2 hf2 en1 en2 en1 pl1 pl2 pl1. hft fft cwstr rsr nfd mr hi-8582, hi-8583 holt integrated circuits 2
functional description control word register the hi-8582/hi-8583 contain a 16-bit control register which is used to configure the device. the control register bits cr0 - cr15 are loaded from bd00 - bd15 when is pulsed low. the control register contents are output on the databus when sel = 1 and is pulsed low. each bit of the control register has the following function: cwstr rsr status register the hi-8582/hi-8583 contain a 9-bit status register which can be interrogated to determine the status of the arinc receivers, data fifos and transmitter. the contents of the status register are output on bd00 - bd08 when the pin is taken low and sel = 0. unused bits are output as zeros. the following table defines the status register bits. rsr hi-8582, hi-8583 sr bit function state description sr0 data ready 0 receiver 1 fifo empty 1 receiver 1 fifo contains valid data resets to zero when all data has been read. pin is the inverse of this bit (receiver 1) sr1 fifo half full 0 receiver 1 fifo holds less than 16 (receiver 1) words 1 receiver 1 fifo holds at least 16 words. pin is the inverse of this bit. sr2 fifo full 0 receiver 1 fifo not full (receiver 1) 1 receiver 1 fifo full. to avoid data loss, the fifo must be read within one arinc word period. pin is the inverse of this bit sr3 data ready 0 receiver 2 fifo empty (receiver 2) 1 receiver 2 fifo contains valid data resets to zero when all data has been read. pin is the inverse of this bit sr4 fifo half full 0 receiver 2 fifo holds less than 16 (receiver 2) words 1 receiver 2 fifo holds at least 16 words. pin is the inverse of this bit. sr5 fifo full 0 receiver 2 fifo not full (receiver 2) 1 receiver 2 fifo full. to avoid data loss, the fifo must be read within one arinc word period. pin is the inverse of this bit sr6 transmitter fifo 0 transmitter fifo not empty empty 1 transmitter fifo empty. sr7 transmitter fifo 0 transmitter fifo not full full 1 transmitter fifo full. pin is the inverse of this bit. sr8 transmitter fifo 0 transmitter fifo contains less than half full 16 words 1 transmitter fifo contains at least 16 words. pin is the inverse of this bit. d/r1 hf1 ff1 d/r2 hf2 ff2 fft hft cr bit function state description cr0 receiver 1 0 data rate = clk/10 select 1 data rate = clk/80 data clock cr1 label memory 0 normal operation read / write 1 load 16 labels using / read 16 labels using / cr2 enable label 0 disable label recognition recognition (receiver 1) 1 enable label recognition cr3 enable label 0 disable label recognition recognition (receiver 2) 1 enable label recognition cr4 enable 0 transmitter 32nd bit is data 32nd bit as parity 1 transmitter 32nd bit is parity cr5 self test 0 the transmitter?s digital outputs are internally connected to the receiver logic inputs 1 normal operation cr6 receiver 1 0 receiver 1 decoder disabled decoder 1 arinc bits 9 and 10 must match cr7 and cr8 cr7 - - if receiver 1 decoder is enabled, the arinc bit 9 must match this bit cr8 - - if receiver 1 decoder is enabled, the arinc bit 10 must match this bit cr9 receiver 2 0 receiver 2 decoder disabled decoder 1 arinc bits 9 and 10 must match cr10 and cr11 cr10 - - if receiver 2 decoder is enabled, the arinc bit 9 must match this bit cr11 - - if receiver 2 decoder is enabled, the arinc bit 10 must match this bit cr12 invert 0 transmitter 32nd bit is odd parity transmitter parity 1 transmitter 32nd bit is even parity cr13 transmitter 0 data rate=clk/10, o/p slope=1.5us data clock select 1 data rate=clk/80, o/p slope=10us cr14 receiver 2 0 data rate=clk/10 data clock select 1 data rate=clk/80 cr15 data 0 scramble arinc data format 1 unscramble arinc data pl1 pl2 en1 en2 holt integrated circuits 3
the hi-8582/hi-8583 guarantee recognition of these levels with a common mode voltage with respect to gnd less than 4v for the worst case condition (4.75v supply and 13v signal level). the tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. if the arinc signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data. receiver logic operation bit timing bit rate pulse rise time pulse fall time pulse width figure 2 shows a block diagram of the logic section of each receiver. the arinc 429 specification contains the following timing specifi- cation for the received data: 100k bps 1% 12k -14.5k bps 1.5 0.5 sec 10 5 sec 1.5 0.5 sec 10 5 sec 5 sec 5% 34.5 to 41.7 sec if the pin is high, the hi-8582/hi-8583 accept signals that meet these specifications and rejects signals outside the tolerances. the way the logic operation achieves this is described below: high speed low speed nfd 3. each data bit must follow its predecessor by not less than 8 samples and no more than 12 samples. in this manner the bit rate is checked. with exactly 1mhz input clock frequency, the acceptable data bit rates are as follows: 83k bps 10.4k bps 125k bps 15.6k bps 4. the word gap timer samples the null shift register every 10 input clocks (80 for low speed) after the last data bit of a valid reception. if the null is present, the word gap counter is incremented. a count of 3 will enable the next reception. high speed low speed data bit rate min data bit rate max if is held low, frequency discrimination is disabled and any data stream totaling 32 bits is accepted even with gaps between bits. the protocol still requires a word gap as defined in 4. above. nfd functional description (cont.) the receivers arinc bus interface figure 1 shows the input circuit for each receiver. the arinc 429 specification requires the following detection levels: one +6.5 volts to +13 volts null +2.5 volts to -2.5 volts zero -6.5 volts to -13 volts state differential voltage 1. key to the performance of the timing checking logic is an ac- curate 1mhz clock source. less than 0.1% error is recom- mended. 2. the sampling shift registers are 10 bits long and must show three consecutive ones, zeros or nulls to be considered valid data. additionally, for data bits, the one or zero in the upper bits of the sampling shift registers must be followed by a null in the lower bits within the data bit time. for a null in the word gap, three consecutive nulls must be found in both the upper and lower bits of the sampling shift register. in this manner the mini- mum pulse width is guaranteed. gnd gnd rin1b or rin2b rin1a or rin2a differential amplifiers ones comparators null zeroes v dd v dd figure 1. arinc receiver input byte 2 data bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bus 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 arinc 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 bit cr15=0 arinc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 bit cr15=1 parity parity sdi sdi label label sdi sdi label label label label label label label label label label label label label label arinc 429 data format control register bit cr15 is used to control how individual bits in the received or transmitted arinc word are mapped to the hi-8582/ hi-8583 data bus during data read or write operations. the following table describes this mapping: data bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bd bus 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 arinc 13 12 11 10 9 31 30 32 12345678 bit cr15=0 byte 1 arinc 16 15 14 13 12 11 10 987654321 bit cr15=1 hi-8582, hi-8583 holt integrated circuits 4
fifo load control sel en control bit / r/w control 32 to 16 driver 32 bit shift register to pins controlbits cr0, cr14 clock option clock clk bit counter and end of sequence parity check 32nd bit data bit clock word gap word gap timer bit clock end start sequence control error clock error detection shift register shift register null zeros shift register ones eos figure 2. receiver block diagram label / decode compare 16x8 label memory 32x32 fifo d/r ff mux contro l control bits hf 0 x 0 x load fifo 1 no 0 x ignore data 1 yes 0 x load fifo 0 x 1 no ignore data 0 x 1 yes load fifo 1 yes 1 no ignore data 1 no 1 yes ignore data 1 no 1 no ignore data 1 yes 1 yes load fifo cr2(3) arinc word cr6(9) arinc word fifo matches bits 9,10 label match cr7,8 (10,11) functional description (cont.) receiver parity the receiver parity circuit counts ones received, including the parity bit. if the result is odd, then a "0" will appear in the 32nd bit. retrieving data once 32 valid bits are recognized, the receiver logic generates an end of sequence (eos). depending upon the state of control register bits cr2-cr11, the received arinc 32-bit word is then checked for correct decoding and label matching before being loaded into the 32 x 32 receive fifo. arinc words which do not meet the necessary 9th and 10th arinc bit or label matching are ignored and are not loaded into the receive fifo. the following table describes this operation. hi-8582, hi-8583 holt integrated circuits 5
cr4,12 figure 3. transmitter block diagram data clock cr13 pl1 pl2 clk tx clk parity generator data and null timer sequencer line driver bit and word gap counter start sequence word counter and fifo control increment word count data clock divider fifo loading sequencer txaout txbout 32 x 32 fifo 32 bit parallel load shift register bit clock word clock address load data bus tx/r entx test hft fft reading labels after the write that changes cr1 from 0 to 1, the next 16 data reads of the selected receiver ( taken low) are labels. is used to read labels for receiver 1, and to read labels for receiver 2. label data is presented on bd0-bd7. when writing to, or reading from the label memory, sel must be a one, all 16 locations should be accessed, and cr1 must be written to zero before returning to normal operation. label recognition must be disabled (cr2/3=0) during the label read sequence. en en1 en2 transmitter fifo operation the fifo is loaded sequentially by first pulsing to load byte 1 and then to load byte 2. the control logic automatically loads the 31 bit word (or 32 bit word if cr4=0) in the next available position of the fifo. if tx/r, the transmitter ready flag is high (fifo empty), then up to 32 words, each 31 or 32 bits long, may be loaded. if tx/r is low, then only the available positions may be loaded. if all 32 positions are full, the flag is asserted and the fifo ignores further attempts to load data. a transmitter fifo half-full flag is provided. when the transmit fifo contains less than 16 words, is high, indicating to the system microprocessor that a 16 arinc word block write sequence can be initiated. in normal operation (cr4=1), the 32nd bit transmitted is a parity bit. odd or even parity is selected by programming control register bit cr12 to a zero or one. if cr4 is programmed to a 0, then all 32-bits of data loaded into the transmitter fifo are treated as data and are transmitted. pl1 pl2 fft hft hft the chip compares the incoming label to the stored labels if label recognition is enabled. if a match is found, the data is processed. if a match is not found, no indicators of receiving arinc data are presented. note that 00(hex) is treated in the same way as any other label value. label bit significance is not changed by the status of control register bit cr15. label bits bd00 - bd07 are always compared to received arinc bits 1 - 8 respectively. after a write that takes cr1 from 0 to 1, the next 16 writes of data ( pulsed low) load label data into each location of the label memory from the bd00 - bd07 pins. the pin is used to write label data for receiver 1 and for receiver 2. loading labels pl pl1 pl2 note that arinc word reception is suspended during the label memory write sequence. once a valid arinc word is loaded into the fifo, then eos clocks the data ready flag flip flop to a "1", or (or both) will go low. the data flag for a receiver will remain low until arinc bytes from that receiver are retrieved and the fifo is empty. this is accomplished by first activating with sel, the byte selector, low to retrieve the first byte and then activating with sel high to retrieve the second byte. retrieves data from receiver 1 and retrieves data from receiver 2. up to 32 arinc words may be loaded into each receiver?s fifo. the ( ) pin will go low when the receiver 1 (2) fifo is full. failure to retrieve data from a full fifo will cause the next valid arinc word received to overwrite the existing data in fifo location 32. a fifo half full flag ( ) goes low if the fifo contains 16 or more received arinc words. the ( ) pin is intended to act as an interrupt flag to the system?s external microprocessor, allowing a 16 word data retrieval routine to be performed, without the user needing to continually poll the hi-8582/hi-8583 status register bits. d/r1 d/r2 en en en1 en2 ff1 ff2 hf1 hf2 hf1 hf2 both label recognition hi-8582, hi-8583 functional description (cont.) holt integrated circuits 6
the hi-8582 has 37.5 ohms in series with each line driver output. the hi-8583 has 10 ohms in series. the hi-8583 is for applications where external series resistance is needed, typically for lightning protection devices. repeater mode of operation allows a data word that has been received by the hi-8582/hi-8583 to be placed directly into the transmitter fifo. repeater operation is similar to normal receiver operation. in normal operation, either byte of a received data word may be read from the receiver latches first by use of sel input. during repeater operation however, the lower byte of the data word must be read first. this is necessary because, as the data is being read, it is also being loaded into transmitter fifo which is always loaded with the lower byte of the data word first. signal flow for repeater operation is shown in the timing diagrams section. please refer to the holt an-300 application note for additional information and recommendations on lightning protection of holt line drivers and line receivers. repeater operation hi-8582-10 and hi-8583-10 the hi-8582-10/hi-8583-10 options are similar to the hi-8582/ hi-8583 with the exception that they allow an external 10 kohm re- sistor to be added in series with each arinc input without affect- ing the arinc input thresholds. this option is especially useful in applications where lightning protection circuitry is also required. each side of the arinc bus must be connected through a 10 kohm series resistor in order for the chip to detect the correct arinc levels. the typical 10 volt differential signal is translated and input to a window comparator and latch. the comparator lev- els are set so that with the external 10 kohm resistors, they are just below the standard 6.5 volt minimum arinc data threshold and just above the standard 2.5 volt maximum arinc null thresh- old. the hi-8582 and hi-8583 may be operated at clock frequencies beyond that required for arinc compliant operation. for operation at master clock (clk) frequencies up to 5mhz, please contact holt applications engineering. high speed operation power supply sequencing master reset ( ) the power supplies should be controlled to prevent large currents during supply turn-on and turn-off. the recommended sequence is v+ followed by v , always ensuring that v+ is the most positive supply. the v- supply is not critical and can be asserted at any time. on a master reset data transmission and reception are immedi- ately terminated, all three fifos are cleared as are the fifo flags at the device pins and in the status register. the control register is not affected by a master reset. dd mr data transmission transmitter parity self test system operation line driver operation when entx goes high, enabling transmission, the fifo positions are incremented with the top register loading into the data transmission shift register. within 2.5 data clocks the first data bit appears at txaout and txbout. the 31 or 32 bits in the data transmission shift register are presented sequentially to the outputs in the arinc 429 format with the following timing: the word counter detects when all loaded positions have been transmitted and sets the transmitter ready flag, tx/r, high. the parity generator counts the ones in the 31-bit word. if control register bit cr12 is set low, the 32nd bit transmitted will make parity odd. if the control bit is high, the parity is even. setting cr4 to a zero bypasses the parity generator, and allows 32 bits of data to be transmitted. if control register bit cr5 is set low, the transmitter serial output data are internally connected to each of the two receivers, bypassing the analog interface circuitry. data is passed unmodified to receiver 1 and inverted to receiver 2. taking test high forces txaout and txbout into the null state regardless of the state of cr5. the two receivers are independent of the transmitter. therefore, control of data exchanges is strictly at the option of the user. the only restrictions are: 1. the received data will be overwritten if the receiver fifo is full and at least one location is not retrieved before the next complete arinc word is received. 2. the transmitter fifo can store 32 words maximum and ignores attempts to load additional data if full. the line driver in the hi-8582/hi-8583 are designed to directly drive the arinc 429 bus. the two arinc outputs (txaout and txbout) provide a differential voltage to produce a +10 volt one, a -10 volt zero, and a 0 volt null. control register bit cr13 controls both the transmitter data rate, and the slope of the differential output signal. no additional hardware is required to control the slope. programming cr13 to zero causes a 100 kbits/s data rate and a slope of 1.5 s on the arinc outputs; a one on cr13 causes a 12.5 kbit/s data rate and a slope of 10 s. timing is set by on-chip resistor and capacitor and tested to be within arinc requirements. arinc data bit time 10 clocks 80 clocks data bit time 5 clocks 40 clocks null bit time 5 clocks 40 clocks word gap time 40 clocks 320 clocks high speed low speed hi-8582, hi-8583 functional description (cont.) holt integrated circuits 7
data rate - example pattern txaout arinc bit txbout null data data data null null word gap bit 1 next word bit 32 bit 31 bit 30 transmitter operation pl2 dwset t dwhld t tx/r t dwhld t pl12 t pl t data bus pl1 tx/r, , hft fft byte 2 valid pl t pl12 t dwset t byte 1 valid selen t ensel t selen t byte 1 dataen t endata t readen t receiver operation d/r hf ff ,, arinc data sel en data bus bit 31 bit 32 selen t d/r t dataen t d/ren t end/r t en t ensel t endata t endata t enen t don't care byte 1 valid byte 2 valid loading control word cwhld t cwset t cwstr t data bus cwstr valid timing diagrams hi-8582, hi-8583 holt integrated circuits 8
label memory read sequence cwstr or en1 en2 data bus set cr1=1 label #1 label #16 set cr1=0 cwstr t cwset t cwhld t endata t label #2 dataen t readen t label memory load sequence cwstr or pl1 pl2 data bus set cr1=1 label #1 label #2 label #16 set cr1=0 cwstr t cwset t cwhld t dwset t dwhld t pl t label t control register read cycle byte select sel rsr data bus selen t dataen t ensel t endata t don't care don't care data valid status register read cycle byte select sel rsr data bus selen t dataen t ensel t endata t don't care don't care data valid timing diagrams (cont.) hi-8582, hi-8583 holt integrated circuits 9
repeater operation timing don't care rin d/r en pl1 pl2 sel txr entx txaout txbout bit 32 don't care d/r t en t d/ren t enen t en t end/r t selen t ensel t enpl t plen t selen t ensel t enpl t plen t tx/r t tx/ren t endat t entx/r t dtx/r t null t bit 1 bit 32 transmitting data arinc bit arinc bit arinc bit pl2 entx txaout txbout diff v (txaout) - txbout) +5v +5v +5v +10v +10v -10v -5v -5v -5v txr pl2en t endat t dtx/r t entx/r t data bit 1 data bit 2 data bit 32 one level zero level null level 90% 90% 10% 10% t fx t rx t fx t rx timing diagrams (cont.) hi-8582, hi-8583 holt integrated circuits 10
supply voltages v ........................................... -0.3v to +7v v+ ...................................................... +12.5v v- ...................................................... -12.5v voltage at pins rin1a, rin1b, rin2a, rin2b ..... -29v to +29v voltage at any other pin ............................... -0.3v to v +0.3v solder temperature (leads) .................... 280 for 10 seconds (package) .......................................... 220 dd dd c c power dissipation at 25c plastic quad flat pack ..................1.5 w, derate 10mw/ c ceramic j-lead cerquad ...... 1.0 w, derate 7mw/ dc current drain per pin .............................................. 10ma operating temperature range (industrial): .... -40c to +85c (military): ..... -55c to +125c c storage temperature range ........................ -65c to +150c absolute maximum ratings note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. hi-8582, hi-8583 holt integrated circuits 11
limits parameter conditions unit symbol differential input voltage: one v common mode voltages 6.5 10.0 13.0 v (rin1a to rin1b, rin2a to rin2b) zero v less than 4v with -13.0 -10.0 -6.5 v null v respect to gnd -2.5 0 2.5 v input resistance: differential r 12 46 k to gnd r 12 38 k to v r 12 38 k input current: input sink i 200 a input source i -450 a input capacitance: differential c 20 pf (guaranteed but not tested) to gnd c 20 pf to v c 20 pf input voltage: input voltage hi v 2.0 v input voltage lo v 0.8 v input current: input sink i 1.5 a input source i -1.5 a input voltage: input voltage hi v 2.0 v input voltage lo v 0.8 v input current: input sink i 1.5 a input source i -1.5 a pull-up current ( pin) i -150 -50 min typ max arinc inputs - pins rin1a, rin1b, rin2a, rin2b bi-directional inputs - pins bd00 - bd15 other inputs ih il nul i g dd h ih il i g dd h ih il ih il ih il ih il pu (rin1a to rin1b, rin2a to rin2b) a pull-down current (test pin) i 50 150 a nfd pd arinc outputs - pins txaout, txbout other outputs operating voltage range operating supply current output voltage: logic "1" output voltage v i = -1.5ma 2.7 v logic "0" output voltage v i = 1.6ma 0.4 v output current: output sink i v = 0.4v 1.6 ma (all outputs & bi-directional pins) output source i v = v - 0.4v -1.0 ma output capacitance: c 15 pf vdd 4.75 5.25 v v+ 9.5 10.5 v v- -9.5 -10.5 v vdd i 4 20 ma arinc output voltage (ref. to gnd) one or zero v no load and magnitude at pin, 4.50 5.00 5.50 v null v v = 5.0 v -0.25 0.25 v arinc output voltage (differential) one or zero v no load and magnitude at pin, 9.0 10.0 11.0 v null v v = 5.0 v -0.5 0.5 v arinc output current i 80 ma v+ i 3.2 16 ma v- i 3.2 16 ma dout nout dd ddif ndif dd out dd2 ee1 oh oh ol ol ol out oh out dd o dd1 dc electrical characteristics v = 5v , gnd = 0v, ta = operating temperature range (unless otherwise specified). dd v+ = 10v, v- = -10v, hi-8582, hi-8583 holt integrated circuits 12
ac electrical characteristics vdd = 5v, v+=10v, v-=-10v, gnd = 0v, ta = oper. temp. range and fclk=1mhz 0.1% with 60/40 duty cycle + limits parameter symbol units min typ max control word timing receiver fifo and label read timing transmitter fifo and label write timing transmission timing line driver output timing pulse width - t 80 ns setup - data bus valid to high t 50 ns hold - high to data bus hi-z t 0 ns delay - start arinc 32nd bit to low: high speed t 16 s low speed t 128 s delay - low to low t 0 ns delay - high to high t 250 350 ns setup - sel to low t 10 ns hold - sel to high t 10 ns delay - low to data bus valid t 60 100 ns delay - high to data bus hi-z t 50 80 ns pulse width - or t 60 ns spacing - high to next low (same arinc word) t 60 ns spacing - high to next low (next arinc word) t 200 ns pulse width - or t 80 ns setup - data bus valid to high t 105 ns hold - high to data bus hi-z t 10 ns spacing - or t 85 ns spacing between label write pulses t 200 ns delay - high to tx/r low t 300 ns spacing - high to entx high t 0 s delay - 32nd arinc bit to tx/r high t 50 ns spacing - tx/r high to entx low t 0 ns line driver transition differential times: high to low t 1.0 1.5 2.0 cwstr cwstr cwstr d/r d/r en en d/r en en en en en1 en2 en en en en pl1 pl2 pl pl pl1 pl2 pl2 pl2 cwstr cwset cwhld d/r d/r d/ren end/r selen ensel endata dataen en enen readen pl dwset dwhld pl12 label tx/r pl2en dtx/r entx/r fx delay - entx high to txaout or txbout: high speed t 25 s delay - entx high to txaout or txbout: low speed t 200 s (high speed, control register cr13 = logic 0) s low to high t 1.0 1.5 2.0 s (low speed, control register cr13 = logic 1) high to low t 5.0 10 15 s low to high t 5.0 10 15 s endat endat rx fx rx repeater operation timing delay - low to low t 0 ns en pl enpl hold - high to high t 0 ns delay - tx/r low to entx high t 0 ns t50 ns 1% pl en plen tx/ren mr master reset pulse width arinc data rate and bit timing hi-8582, hi-8583 holt integrated circuits 13
additional hi-8582 / hi-8583 pin configurations 7- 6 - rin2b 5 - rin2a 4 - rin1b 3 - rin1a 2 - vdd 1 - n/c 52 - test 51 - 50 - txclk 49 - clk 48 - 47 - n/c d/r1 mr rsr 46 - n/c 45 - 44 - entx 43-v+ 42 - txbout 41 - txaout 40-v- 39 - 38 - 37 - tx/r 36 - 35 - 34 - bd00 cwstr fft hft pl2 pl1 bd10 - 21 bd09 - 22 bd08 - 23 bd07 - 24 bd06 - 25 n/c-26 gnd-27 -28 bd05 - 29 bd04 - 30 bd03 - 31 bd02 - 32 bd01 - 33 nfd ff1 hf1 d/r2 ff2 hf2 en1 en2 -8 -9 -10 -11 -12 sel - 13 -14 -15 bd15 - 16 bd14 - 17 bd13 - 18 bd12 - 19 bd11 - 20 hi-8582cji hi-8582cjt & hi-8583cji hi-8583cjt ordering information hi - - 85xx xx x x xx 10 ohms 27.5 ohms 37.5 ohms 0 part number 8582 8583 output series resistance built-in required externally package description 52 pin cerquad j lead (52u) not available pb-free part number cj 52 pin plastic quad flat pack pqfp (52pqs) pq temperature range burn in -40c to +85c no -55c to +125c no t part number t i flow i lead finish part number 100% matte tin (pb-free, rohs compliant) f tin / lead (sn / pb) solder blank input series resistance built-in required externally part number 25 kohm 10 kohm -10 35 kohm 0 no dash number 52 - pin cerquad j-lead (see page 1 for additional pin configuration) hi-8582, hi-8583 holt integrated circuits 14
hi-8582 / hi-8583 package dimensions 52-pin j-lead cerquad inches (millimeters) package type: 52u bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .019 .002 (.483 .051) 8 7 1 52 47 .788 (20.0) .720 .010 (18.29 .25) .750 .007 (19.05 .18) .190 (4.826) max
.050 (1.27) bsc sq. max 52-pin plastic quad flat pack (pqfp) inches (millimeters) package type: 52pqs d etail a see detail a 0 7 .520 (13.2) bsc sq .394 (10.0) bsc sq .063 (1.6) typ .084 .013 (2.13 .32) .079 .008 (2.00 .20) .008 (.20) min .005 (.13) r min r min .008 .003 (.215 .085) .0256 (.65) bsc .012 .003 (.30 .08) .035 .006 (.88 .15) bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) holt integrated circuits 15

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